Programmable integrated circuits are known in the art and include programmable logic devices ("PLDs"), Programmable Array Logic ("PALs"), and Programmable Logic Arrays ("PLAs"). Each of these programmable circuits provides an input AND logic plane followed by an OR logic plane. An output function can thus be calculated which is the sum of the products of the input terms. The logic planes are usually programmable such that the initial general layout of the planes may be customized for a particular application.
A more general approach to programmable circuits involves providing an array of distinct, uncommitted logic cells in a Programmable Gate Array ("PGA"). A programmable interconnect network is provided to interconnect the cells, and to provide data input to, and output from, the array. Customization or programming of the otherwise generally-designed logic cells and interconnect network is performed for a particular application. One such array is a Mask Programmable Gate Array ("MPGA"), wherein the configuration of the cells and the wiring network occurs when adding the final layers of metallization to an integrated circuit. A modified approach involves the use of laser-directed energy to customize the metallization pattern. Another such array is a Field Programmable Gate Array ("FPGA"), wherein the configuration can be performed by a user, in the "field." Such configuration may be effected by using electrically programmable fusible links, antifuses, memory-controlled transistors, floating-gate transistors, or the like.
Regardless of the type of programing employed, the capabilities and efficiency of the array are determined primarily by the types and amounts of uncommitted resources provided in the logic cells and the interconnect network. One prior art approach to programmable interconnect networks employs a large group of lines (i.e., 25), including a mix of general interconnect lines and long lines, for each row or column of logic cells (see, e.g., U.S. Pat. No. 5,260,881 assigned to Advanced Micro Devices, Inc.). Numerous programmable switches and programmable interconnection points are placed within these groups of lines to segment the lines and to provide signals between the segmented lines. FIGS. 4 and 5 therein depict the distribution and types of lines, and FIGS. 1, 6 and 17-19 depict the placement and structure of the switches and interconnect points.
Another prior art approach employs a smaller number (i.e., 4) of buses for each row or column of logic cells (see, e.g., U.S. Pat. No. 5,298,805 assigned to National Semiconductor Corporation). As shown in FIGS. 9 and 23B therein, a regular pattern of switches (i.e., switching repeaters) is employed for providing signals between collinear conductors of each bus and between conductors of adjacent buses. The networks disclosed in U.S. Patents Nos. 4,642,487 and 4,870,302 assigned to Xilinx, Inc., also disclose buses and regular switch patterns therein. Improved bus segmenting patterns are disclosed in U.S. Pat. Nos. 5,187,393 and 5,073,729 assigned to Actel Corporation.
Manufacturers of programmable gate arrays face a tradeoff between the amount of uncommitted network resources supplied (which is directly proportional to the design flexibility of the array afforded a user), and the efficiency of the array, i.e., the amount of network resources actually employed in a user design. To supply the user with the maximum amount of design flexibility, a large amount of uncommitted resources in a highly generalized, regular arrangement is desirable. However, many of these resources remain unused following programming, thus wasting chip space and possibly power. Conversely, to achieve high efficiency, a reduced amount of uncommitted resources is desirable. However, this approach would adversely impact the design flexibility of the array.
Thus, improvements to the prior art approaches to interconnect networks are required which minimize the amount of unused resources following array programming. These improvements should simultaneously afford the array user or programmer a suitable level of design flexibility. These improvements should thus result in a manageable amount of programmable resources (thereby increasing efficiency) being arranged in a way which provides a satisfactory level of design flexibility to an array user.